ANALYSIS OF LOGARITHMIC ANALOG-TO-DIGITAL CONVERTER WITH SUCCESSIVE APPROXIMATION TAKING INTO ACCOUNT PARASITIC CAPACITANCES

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DOI

Adam Szcześniak

adam_szczesniak@o2.pl

Zynowij Myczuda

z_mychuda@ukr.net

Abstract

This article is a presentation of analysis of logarithmic analog-to-digital converter (LADC) with successive approximation taking into account parasitic capacitances of the converter. For the assumed parameters of converter structure, mathematical analysis with chosen capacitances of accumulative capacitors has been conducted. A criterion for choosing capacitances of accumulative capacitors has been determined.

Keywords:

analog-to-digital converter, logarithm, approximation, division, charge, accuracy

References

Article Details

Szcześniak, A. ., & Myczuda, Z. . (2017). ANALYSIS OF LOGARITHMIC ANALOG-TO-DIGITAL CONVERTER WITH SUCCESSIVE APPROXIMATION TAKING INTO ACCOUNT PARASITIC CAPACITANCES. Informatyka, Automatyka, Pomiary W Gospodarce I Ochronie Środowiska, 7(2), 110–114. https://doi.org/10.5604/01.3001.0010.4851