BIT ERROR NOTIFICATION AND ESTIMATION IN REDUNDANT SUCCESSIVE-APPROXIMATION ADC
Serhii Zakharchenko
Vinnytsia National Technical University, Department of Computer Facilities, Vinnytsia, Ukraine (Ukraine)
http://orcid.org/0000-0003-3977-2908
Roman Humeniuk
romchik003@gmail.comVinnytsia National Technical University, Department of Computer Facilities (Ukraine)
https://orcid.org/0000-0001-9986-8894
Abstract
The article is devoted to research on the possibilities to use redundant number systems for bit error notification in a successive-approximation ADC during the main conversion mode. The transfer function of a successive-approximation ADC with a non-binary radix is analyzed. If the radix is less than 2, not all possible code combinations appear on the converter output. The process of formation of unused combinations is investigated. The relationship between the bit’s deviations and the list of unused combinations is established. The possibilities of estimating the bit error value without interrupting the process of analog-to-digital conversion is considered.
Keywords:
successive-approximation ADC, redundant number systems, ADC transfer functionReferences
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Authors
Serhii ZakharchenkoVinnytsia National Technical University, Department of Computer Facilities, Vinnytsia, Ukraine Ukraine
http://orcid.org/0000-0003-3977-2908
Authors
Roman Humeniukromchik003@gmail.com
Vinnytsia National Technical University, Department of Computer Facilities Ukraine
https://orcid.org/0000-0001-9986-8894
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