The article analyzes the physical processes that occur in spin-valve structures during recording process which occurs in high-speed magnetic memory devices. Considered are devices using magnetization of the ferromagnetic layer through transmitting magnetic moment by polarized spin (STT-MRAM). Basic equations are derived to model the information recording process in the model of symmetric binary channel. Because the error probability arises from the magnetization process, a model of the magnetization process is formed, which is derived from the Landau-Lifshitz-Gilbert equations under the assumption of a single-domain magnet. The choice of a single-domain model is due to the nanometer size of the flat magnetic layer. The developed method of modeling the recording process determines the dependence of such characteristics as the bit error probability and the rate of recording on two important technological characteristics of the recording process: the value of the current and its duration. The end result and the aim of the simulation is to determine the optimal values of the current and its duration at which the speed of the recording process is the highest for a given level of error probability. The numerical values of the transmission rate and error probability were obtained for a wide range of current values (10–1500 μA) and recording time of one bit (1–70 ns), and generally correctly describe the process of information transmission. The calculated data were compared with the technical characteristics of existing industrial devices and devices which are the object of the scientific research. The resulting model can be used to simulate devices using different values of recording currents: STT-MRAM series chips using low current values (500-100 μA), devices in the stage of technological design and using medium current values (100–500 μA) and devices that are the object of experimental scientific research and use high currents (500–1000 μA). The model can also be applied to simulate devices with different data rates, which have different requirements for both transmission speed and bit error probability. In this way, the model can be applied to both high-speed memory devices in computer systems and signal sensors, which are connected to sensor networks or connected to the IoT.


STT-MRAM; spin-polarized current; binary symmetric channel

Alioto M.: STT-MRAM memories for IoT applications. Challenges and opportunities at circuit level and above International Symposium on VLSI Technology, Systems and Application VLSI-TS, Hsinchu, 2017, []. DOI:

Apalkov D., Dieny B., Slaughter J.: Magnetoresistive Random Access memory. Proc. of the IEEE 109/2017, 1796–1830, []. DOI:

Bhatti S. et al.: Spintronic based random access memory: a review. Materials Today 6(9)/2017, 530–548, []. DOI:

Cai K., Immink K. A. S.: Cascaded channel modeling, analysis, and hybrid decoding for spin-torque transfer magnetic random access memory. IEEE Transactions on Magnetics 53(11)/2017, 1–11, []. DOI:

Cai H.: High performance MRAM with spin-transfer-torque and voltage-controlled magnetic anisotropy effects. Applied Sciences 7(9)/2017, 929–943, []. DOI:

Chung S. et al.: 4Gbit Density STT-MRAM using Perpendicular MTJ Realized with Compact Cell Structure IEEE International Electron Devices Meeting IEDM, San Francisco 2016, []. DOI:

Greenan K., Miller E.: Reliability mechanisms for file systems using non-volatile memory as a metadata store. International conference on Embedded software EMSOFT, Seoul 2006, []. DOI:

Lai H. et al.: STT-MRAM application on IoT data privacy protection system. IEEE International Conference on Consumer Electronics ICCE-TW, Taichung 2018, [].

Lee K.: Bit error rate engineering for spin-transfer-torque MRAM. International Integrated Reliability Workshop. International IEEE Conference, South Lake Tahoe 2014, [].

Lee Y. et al.: Embedded STT-MRAM in28-nm FDSOI Logic Process for Industrial MCU/IoT Application. IEEE Symposium on VLSI Technology, Honolulu 2018, []. DOI:

Sun J.Z., Xu, Y.: Handbook of Spintronics. Springer, Chicago 2016.

Sverdlov V., Makarov A.,Selberherr S.: Switching current reduction in advanced spin-orbit torque MRAM. Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon EUROSOL-ULIS, 2018, []. DOI:

Vatajelu E. et al.: STT MRAM-Based PUF’s. Design, Automation & Test in Europe Conference & Exhibition DATE, Grenoble 2015, []. DOI:

Wang P. et al.: Development of STT-MRAM for embedded memory applications. IEEE International Magnetic Conference INTERMAG, Dublin 2017, []. DOI:

Yamauchi T.: Prospect of embedded non-volatile memory in the smart society. VLSI Technology, System and Application: International Symposium, Hsinchu 2015, []. DOI:


Published : 2020-03-30

Politanskyi, R., Vistak, M., Veryga, A., & Ruda, T. (2020). MODELLING OF SPINTRONIC DEVICES FOR APPLICATION IN RANDOM ACCESS MEMORY . Informatyka, Automatyka, Pomiary W Gospodarce I Ochronie Środowiska, 10(1), 62-65.

Ruslan Politanskyi
Maria Vistak 
Danylo Halytsky Lviv National Medical University, Faculty of Pharmacy, Department of Biophysics  Ukraine
Andriy Veryga 
Yuriy Fedkovych Chernivtsi National University, Physical, Technical and Computer Sciences Institute, Department of Radio Engineering and Information Security  Ukraine
Tetyana Ruda 
Yuriy Fedkovych Chernivtsi National University, Physical, Technical and Computer Sciences Institute, Department of Radio Engineering and Information Security  Ukraine