ARCHITECTURAL AND STRUCTURAL AND FUNCTIONAL FEATURES OF THE ORGANIZATION OF PARALLEL-HIERARCHICAL MEMORY

Leonid Timchenko

tumchenko_li@gsuite.duit.edu.ua
State University of Infrastructure and Technology (Ukraine)
https://orcid.org/0000-0001-5056-5913

Natalia Kokriatska


State University of Infrastructure and Technology (Ukraine)
https://orcid.org/0000-0003-0090-3886

Volodymyr Tverdomed


State University of Infrastructure and Technology (Ukraine)
https://orcid.org/0000-0002-0695-1304

Iryna Yepifanova


Vinnytsia National Technical Unіversity (Ukraine)
https://orcid.org/0000-0002-0391-9026

Yurii Didenko


State University of Infrastructure and Technology (Ukraine)
https://orcid.org/0009-0008-1033-4238

Dmytro Zhuk


State University of Infrastructure and Technology, Kyiv, Ukraine (Ukraine)
https://orcid.org/0000-0001-8951-5542

Maksym Kozyr


State University of Infrastructure and Technology (Ukraine)
https://orcid.org/0009-0007-2564-6552

Iryna Shakhina


Vinnytsia Mykhailo Kotsiubynskyi State Pedagogical University (Ukraine)
https://orcid.org/0000-0002-4318-6189

Abstract

Parallel hierarchical memory (PI memory) is a new type of memory that is designed to improve the performance of parallel computing systems. PI memory is composed of two blocks: a mask RAM and a tail element RAM. The mask RAM stores the masks that are used to encode the information, while the tail element RAM stores the actual information. The address block of the PI memory is responsible for generating the physical addresses of the cells where the tail elements and their masks are stored. The address block also stores the field of addresses where the array was written and associates this field of addresses with the corresponding external address used to write the array. The proposed address block structure is able to efficiently generate the physical addresses of the cells where the tail elements and their masks are stored. The address block is also able to store the field of addresses where the array was written and associate this field of addresses with the corresponding external address used to write the array. The proposed address block structure has been implemented in a prototype PI memory. The prototype PI memory has been shown to be able to achieve significant performance improvements over traditional memory architectures. The paper will present a detailed description of the PI transformation algorithm, a description of the different modes of addressing organization that can be used in PI memory, an analysis of the efficiency of parallel-hierarchical memory structures, and a discussion of the challenges and future research directions in the field of PI memory.


Keywords:

parallel hierarchical memory, PI memory, address block, mask RAM, tail element RAM, performance improvement

Aboutabl A. E., Elsayed M. N.: A Novel Parallel Algorithm for Clustering Documents Based on the Hierarchical Agglomerative Approach. International Journal of Computer Science & Information Technology – IJCSIT 3(2), 2011, 152–163.
  Google Scholar

Bisikalo O. et al.: Parameterization of the Stochastic Model for Evaluating Variable Small Data in the Shannon Entropy Basis. Entropy 25(2), 2023, 184.
  Google Scholar

Bykov M. et al.: Neural network modelling by rank configurations. Proc. of SPIE 10808, 2018, 1080821.
  Google Scholar

Kim S., Wunsch D. C.: A GPU based Parallel Hierarchical Fuzzy ART clustering. IJCNN IEEE, 2011, 2778–2782.
  Google Scholar

Kohonen T.: Self Organization and Associative Memory: Third Edition. Springer-Verlag, New York, 1989.
  Google Scholar

Kovtun V., Izonin I.: Study of the Operation Process of the E-Commerce Oriented Ecosystem of 5Ge Base Station, Which Supports the Functioning of Independent Virtual Network Segments. Journal of Theoretical and Applied Electronic Commerce Research 16(7), 2021, 2883–2897.
  Google Scholar

Kukharchuk V. V. et al.: Features of the angular speed dynamic measurements with the use of an encoder. Informatyka, Automatyka, Pomiary w Gospodarce i Ochronie Srodowiska – IAPGOS 12(3), 2022, 20–26.
  Google Scholar

Kukharchuk V. V. et al.: Information Conversion in Measuring Channels with Optoelectronic Sensors. Sensors 22(1), 2022, 271.
  Google Scholar

Kuusilinna K. et al.: Configurable parallel memory architecture for multimedia computers, Journal of Systems Architecture 47(14–15), 2002, 1089–1115.
  Google Scholar

Kvуetnyy R. et al.: Inverse correlation filters of objects features with optimized regularization for image processing. Proc. SPIE 12476, 2022, 124760Q.
  Google Scholar

Li Z., Li K., Xiao D., Yang L.: An Adaptive Parallel Hierarchical Clustering Algorithm. Perrott, R., Chapman, B.M., Subhlok, J., de Mello, R.F., Yang, L.T. (eds): High Performance Computing and Communications. HPCC 2007. Lecture Notes in Computer Science 4782. Springer, Berlin, Heidelberg 2007.
  Google Scholar

Nere A., Lipasti M.: Optimizing Hierarchical Algorithms for GPGPUs. Master's Project Report. University of Wisconsin Madison, 2010.
  Google Scholar

Orazayeva A. et al.: Biomedical image segmentation method based on contour preparation, Proc. SPIE 12476, 2022, 1247605.
  Google Scholar

Osman A. A. M.: A Multi-Level WEB Based Parallel Processing System: A Hierarchical Volunteer Computing Approach. World Academy of Science, Engineering and Technology 13, 2006, 66–71.
  Google Scholar

Pavlov S. V. et al.: The use of Bayesian methods in the task of localizing the narcotic substances distribution. International Scientific and Technical Conference on Computer Sciences and Information Technologies 2, 2019, 8929835, 60–63.
  Google Scholar

Rajasekaran S.: Efficient Parallel Hierarchical Clustering Algorithms. IEEE Transactions on Parallel and Distributed Systems 16(6), 2005, 497–502.
  Google Scholar

Romanyuk S. A. et al.: Using lights in a volume-oriented rendering. Proc. SPIE 10445, 2017, 104450U.
  Google Scholar

Rose K.: Deterministic Annealing, Clustering and Optimization. Ph.D. Thesis, California Institute of Technology, Pasadena, 1991.
  Google Scholar

Sobota B.: Parallel Hierarchical Model of Visualization Computing. Journal of Information, Control and Management Systems 5(2), 2007, 345–350.
  Google Scholar

Sudarshan R. Lee S. E.: A Parallel Hierarchical Solver for the Poisson Equation, May 14, 2003,.
  Google Scholar

Timchenko L. et al.: New methods of network modelling using parallel-hierarchical networks for processing data and reducing erroneous calculation risk. CEUR Workshop 2805, 2020, 201–212.
  Google Scholar

Timchenko L. I., Kokriatskaia N. I., Pavlov S. V., Tverdomed V.: Method of indicators forecasting of biomedical images using a parallel-hierarchical network. Proc. of SPIE 11176, 2019, 111762Q.
  Google Scholar

Timchenko L. I.: A multistage parallel-hierarchic network as a model of a neuronlike computation scheme. Cybern Syst Anal. 36, 2000, 251–267.
  Google Scholar

Tolegen G., Toleu A., Mamyrbayev O., Mussabayev R.: Neural Named Entity Recognition for Kazakh. Lecture Notes in Computer Science 13452, 2023, 3–15.
  Google Scholar

Tymkovych M. et al: Ice crystals microscopic images segmentation based on active contours. IEEE 39th International Conference on Electronics and Nanotechnology – ELNANO 2019, 493–496 [https://doi.org/10.1109/ELNANO.2019.8783332].
  Google Scholar

Vasilevskyi O. et al.: A new approach to assessing the dynamic uncertainty of measuring devices. Proc. of SPIE 10808, 2018, 108082E.
  Google Scholar

Vysotska O. V., Nosov K.: An approach to determination of the criteria of harmony of biological objects. Proc. of SPIE, 10808, 2018, 108083B
  Google Scholar

Wójcik W., Pavlov S., Kalimoldayev M.: Information Technology in Medical Diagnostics II. Taylor & Francis Group, CRC Press, Balkema book, London 2019.
  Google Scholar

Ybytayeva G. et al.: Creating a Thesaurus "Crime-Related Web Content" Based on a Multilingual Corpus. CEUR Workshop Proceedings 3396, 2023, 77–87.
  Google Scholar

Zeki S.: A Vision of the Brain. Blackwell Scientific Publications, Oxford 1993.
  Google Scholar

Zhao X., Guo Y., Feng Z., Hu S.: Parallel Hierarchical Cross Entropy Optimization for On-Chip Decap Budgeting. Design Automation Conference, Anaheim, CA, USA, 2010, 843–848.
  Google Scholar

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Published
2024-03-31

Cited by

Timchenko, L., Kokriatska, N., Tverdomed, V., Yepifanova, I., Didenko, Y., Zhuk, D., … Shakhina, I. (2024). ARCHITECTURAL AND STRUCTURAL AND FUNCTIONAL FEATURES OF THE ORGANIZATION OF PARALLEL-HIERARCHICAL MEMORY. Informatyka, Automatyka, Pomiary W Gospodarce I Ochronie Środowiska, 14(1), 46–52. https://doi.org/10.35784/iapgos.5615

Authors

Leonid Timchenko 
tumchenko_li@gsuite.duit.edu.ua
State University of Infrastructure and Technology Ukraine
https://orcid.org/0000-0001-5056-5913

Authors

Natalia Kokriatska 

State University of Infrastructure and Technology Ukraine
https://orcid.org/0000-0003-0090-3886

Authors

Volodymyr Tverdomed 

State University of Infrastructure and Technology Ukraine
https://orcid.org/0000-0002-0695-1304

Authors

Iryna Yepifanova 

Vinnytsia National Technical Unіversity Ukraine
https://orcid.org/0000-0002-0391-9026

Authors

Yurii Didenko 

State University of Infrastructure and Technology Ukraine
https://orcid.org/0009-0008-1033-4238

Authors

Dmytro Zhuk 

State University of Infrastructure and Technology, Kyiv, Ukraine Ukraine
https://orcid.org/0000-0001-8951-5542

Authors

Maksym Kozyr 

State University of Infrastructure and Technology Ukraine
https://orcid.org/0009-0007-2564-6552

Authors

Iryna Shakhina 

Vinnytsia Mykhailo Kotsiubynskyi State Pedagogical University Ukraine
https://orcid.org/0000-0002-4318-6189

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