ARCHITECTURAL AND STRUCTURAL AND FUNCTIONAL FEATURES OF THE ORGANIZATION OF PARALLEL-HIERARCHICAL MEMORY
Leonid Timchenko
tumchenko_li@gsuite.duit.edu.uaState University of Infrastructure and Technology (Ukraine)
https://orcid.org/0000-0001-5056-5913
Natalia Kokriatska
State University of Infrastructure and Technology (Ukraine)
https://orcid.org/0000-0003-0090-3886
Volodymyr Tverdomed
State University of Infrastructure and Technology (Ukraine)
https://orcid.org/0000-0002-0695-1304
Iryna Yepifanova
Vinnytsia National Technical Unіversity (Ukraine)
https://orcid.org/0000-0002-0391-9026
Yurii Didenko
State University of Infrastructure and Technology (Ukraine)
https://orcid.org/0009-0008-1033-4238
Dmytro Zhuk
State University of Infrastructure and Technology, Kyiv, Ukraine (Ukraine)
https://orcid.org/0000-0001-8951-5542
Maksym Kozyr
State University of Infrastructure and Technology (Ukraine)
https://orcid.org/0009-0007-2564-6552
Iryna Shakhina
Vinnytsia Mykhailo Kotsiubynskyi State Pedagogical University (Ukraine)
https://orcid.org/0000-0002-4318-6189
Abstract
Parallel hierarchical memory (PI memory) is a new type of memory that is designed to improve the performance of parallel computing systems. PI memory is composed of two blocks: a mask RAM and a tail element RAM. The mask RAM stores the masks that are used to encode the information, while the tail element RAM stores the actual information. The address block of the PI memory is responsible for generating the physical addresses of the cells where the tail elements and their masks are stored. The address block also stores the field of addresses where the array was written and associates this field of addresses with the corresponding external address used to write the array. The proposed address block structure is able to efficiently generate the physical addresses of the cells where the tail elements and their masks are stored. The address block is also able to store the field of addresses where the array was written and associate this field of addresses with the corresponding external address used to write the array. The proposed address block structure has been implemented in a prototype PI memory. The prototype PI memory has been shown to be able to achieve significant performance improvements over traditional memory architectures. The paper will present a detailed description of the PI transformation algorithm, a description of the different modes of addressing organization that can be used in PI memory, an analysis of the efficiency of parallel-hierarchical memory structures, and a discussion of the challenges and future research directions in the field of PI memory.
Keywords:
parallel hierarchical memory, PI memory, address block, mask RAM, tail element RAM, performance improvementReferences
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Authors
Leonid Timchenkotumchenko_li@gsuite.duit.edu.ua
State University of Infrastructure and Technology Ukraine
https://orcid.org/0000-0001-5056-5913
Authors
Natalia KokriatskaState University of Infrastructure and Technology Ukraine
https://orcid.org/0000-0003-0090-3886
Authors
Volodymyr TverdomedState University of Infrastructure and Technology Ukraine
https://orcid.org/0000-0002-0695-1304
Authors
Iryna YepifanovaVinnytsia National Technical Unіversity Ukraine
https://orcid.org/0000-0002-0391-9026
Authors
Yurii DidenkoState University of Infrastructure and Technology Ukraine
https://orcid.org/0009-0008-1033-4238
Authors
Dmytro ZhukState University of Infrastructure and Technology, Kyiv, Ukraine Ukraine
https://orcid.org/0000-0001-8951-5542
Authors
Maksym KozyrState University of Infrastructure and Technology Ukraine
https://orcid.org/0009-0007-2564-6552
Authors
Iryna ShakhinaVinnytsia Mykhailo Kotsiubynskyi State Pedagogical University Ukraine
https://orcid.org/0000-0002-4318-6189
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