Using FPGA for modelling and generating chaotic processes

This work presents a comprehensive approach to the implementation of two chaotic dynamic systems – Nose–Hoover and Rikitake – on an FPGA platform. Initially, the systems were modeled in a Python environment using the Euler method, which allowed for the verification of chaotic behavior and an assessment of the impact of the integration step on stability. A comparison of time series and phase portraits confirmed the persistent chaotic nature of both systems within a defined parameter range. Next, a Verilog-based implementation using fixed-point arithmetic (Q16.16) was developed and tested in ModelSim. Simulation results showed a close match with the Python models, indicating a correct choice of bit width and Euler method settings. For real-time data transmission, UART modules and intermediate converters were used to scale Q16.16 outputs to an 8-bit format. This approach enables tracking and recording of computations on a personal computer while maintaining real-time chaotic dynamics. The experimental results confirm that the Nose–Hoover and Rikitake systems can be successfully implemented on an FPGA with limited bit width without significant loss of chaotic properties. This approach has potential applications in cryptography, secure communication, and high-performance pseudorandom signal generators, where flexibility, energy efficiency, and real-time processing are essential.