DESIGN OF 7-BIT LOW-POWER, LOW AREA A/D CONVERTER IN SUBMICRON PROCESS FOR MULTICHANNEL SYSTEMS

Piotr Otfinowski

potfin@agh.edu.pl
Akademia Górniczo-Hutnicza im. Stanisława Staszica w Krakowie, Wydział Elektrotechniki, Automatyki, Informatyki i Elektroniki, Katedra Metrologii (Poland)

Piotr Kmon


Akademia Górniczo-Hutnicza im. Stanisława Staszica w Krakowie, Wydział Elektrotechniki, Automatyki, Informatyki i Elektroniki, Katedra Metrologii (Poland)

Rafał Kłeczek


Akademia Górniczo-Hutnicza im. Stanisława Staszica w Krakowie, Wydział Elektrotechniki, Automatyki, Informatyki i Elektroniki, Katedra Metrologii (Poland)

Abstract

The design of analog-to-digital converter implemented in CMOS 180 nm technology has been presented in this paper. The successive approximation architecture with charge redistribution has been chosen. Much emphasis was placed on limiting the area occupancy of the whole chip so as its power consumption, which makes the described circuit suitable for multichannel applications. The presented converter achieves 3 MS/s sampling rate with 7-bit resolution at 77 μW and occupies only 90 x 95 μm2.


Keywords:

SAR ADC, charge redistribution, successive approximation converter

Chang Y., Wang C., Wang C.: A 8-bit 500-KS/s low power SAR ADC for biomedical applications. IEEE Asian Solid-State Circuits Conference, 2007, pp. 228–231.
  Google Scholar

Elzakker, M., et al.: A 10-bit Charge-Redistribution ADC Consuming 1.9 u W at 1 MS/s. IEEE Journal of Solid-State Circuits, vol. 45 , no. 5, pp: 1007 – 1015.
DOI: https://doi.org/10.1109/JSSC.2010.2043893   Google Scholar

Grybos P., Kmon P., Zoladz M., Szczygiel R., Kachel M., Lewandowski M., Blasiak T.: 64 Channel Neural Recording Amplifier with Tunable Bandwidth in 180 nm CMOS Technology. Metrol. Meas. Syst., Vol. XVIII, No. 4, pp. 631-644.
  Google Scholar

Otfinowski P., Gryboś P., Kłeczek R.: A 10-bit 3MS/s low-power charge redistribution ADC in 180nm CMOS for neural application. MIXDES 2011, Proceedings of the 18th international conference, s. 197–200.
  Google Scholar

Rivetti A., Anelli G., Anghinolfi F., Mazza G.: A low-power 10-bit ADC in a 0.25-μm CMOS: design considerations and test results. IEEE Trans. on Nuclear Science, vol. 48, no. 4, pp. 1225–1228.
DOI: https://doi.org/10.1109/23.958755   Google Scholar

Szczygiel R., Grybos P., Maj P., Tsukiyama A., Matsushita K., Taguchi T.: RG64—High Count Rate Low Noise Multichannel ASIC With Energy Window Selection and Continuous Readout Mode. IEEE Trans. on Nuclear Science, vol. 56, no. 2, pp. 487–495.
DOI: https://doi.org/10.1109/TNS.2008.2012345   Google Scholar

Zhu Y., et al.: A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS. IEEE Journal of Solid-State Circuits, vol. 45, no. 6, pp. 1111-1121.
DOI: https://doi.org/10.1109/JSSC.2010.2048498   Google Scholar


Published
2013-05-16

Cited by

Otfinowski, P. ., Kmon, P., & Kłeczek, R. . (2013). DESIGN OF 7-BIT LOW-POWER, LOW AREA A/D CONVERTER IN SUBMICRON PROCESS FOR MULTICHANNEL SYSTEMS. Informatyka, Automatyka, Pomiary W Gospodarce I Ochronie Środowiska, 3(2), 18–21. https://doi.org/10.35784/iapgos.1447

Authors

Piotr Otfinowski 
potfin@agh.edu.pl
Akademia Górniczo-Hutnicza im. Stanisława Staszica w Krakowie, Wydział Elektrotechniki, Automatyki, Informatyki i Elektroniki, Katedra Metrologii Poland

Authors

Piotr Kmon 

Akademia Górniczo-Hutnicza im. Stanisława Staszica w Krakowie, Wydział Elektrotechniki, Automatyki, Informatyki i Elektroniki, Katedra Metrologii Poland

Authors

Rafał Kłeczek 

Akademia Górniczo-Hutnicza im. Stanisława Staszica w Krakowie, Wydział Elektrotechniki, Automatyki, Informatyki i Elektroniki, Katedra Metrologii Poland

Statistics

Abstract views: 125
PDF downloads: 93