DESIGN OF 7-BIT LOW-POWER, LOW AREA A/D CONVERTER IN SUBMICRON PROCESS FOR MULTICHANNEL SYSTEMS
Piotr Otfinowski
potfin@agh.edu.plAkademia Górniczo-Hutnicza im. Stanisława Staszica w Krakowie, Wydział Elektrotechniki, Automatyki, Informatyki i Elektroniki, Katedra Metrologii (Poland)
Piotr Kmon
Akademia Górniczo-Hutnicza im. Stanisława Staszica w Krakowie, Wydział Elektrotechniki, Automatyki, Informatyki i Elektroniki, Katedra Metrologii (Poland)
Rafał Kłeczek
Akademia Górniczo-Hutnicza im. Stanisława Staszica w Krakowie, Wydział Elektrotechniki, Automatyki, Informatyki i Elektroniki, Katedra Metrologii (Poland)
Abstract
The design of analog-to-digital converter implemented in CMOS 180 nm technology has been presented in this paper. The successive approximation architecture with charge redistribution has been chosen. Much emphasis was placed on limiting the area occupancy of the whole chip so as its power consumption, which makes the described circuit suitable for multichannel applications. The presented converter achieves 3 MS/s sampling rate with 7-bit resolution at 77 μW and occupies only 90 x 95 μm2.
Keywords:
SAR ADC, charge redistribution, successive approximation converterReferences
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Authors
Piotr Otfinowskipotfin@agh.edu.pl
Akademia Górniczo-Hutnicza im. Stanisława Staszica w Krakowie, Wydział Elektrotechniki, Automatyki, Informatyki i Elektroniki, Katedra Metrologii Poland
Authors
Piotr KmonAkademia Górniczo-Hutnicza im. Stanisława Staszica w Krakowie, Wydział Elektrotechniki, Automatyki, Informatyki i Elektroniki, Katedra Metrologii Poland
Authors
Rafał KłeczekAkademia Górniczo-Hutnicza im. Stanisława Staszica w Krakowie, Wydział Elektrotechniki, Automatyki, Informatyki i Elektroniki, Katedra Metrologii Poland
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