DESIGN OF 7-BIT LOW-POWER, LOW AREA A/D CONVERTER IN SUBMICRON PROCESS FOR MULTICHANNEL SYSTEMS
Article Sidebar
Open full text
Published:
May 16, 2013
Issue Vol. 3 No. 2 (2013)
Articles
-
OVERVIEW OF METHODS FOR SYNCHRONIZING WITH THE POWER GIRD (PLL) FOR POWER CONVERTERS
5-8
-
DATA REDUCTION VERSUS FEATURE SELECTION IN APPLICATION OF DAILY MAXIMUM POWER LOAD FORECASTING
9-12
-
MAGNETIC THERAPY: REMOTE CONTROLLING MICROPROCESSOR SYSTEM FOR MAGNETOTHERAPY
13-17
-
DESIGN OF 7-BIT LOW-POWER, LOW AREA A/D CONVERTER IN SUBMICRON PROCESS FOR MULTICHANNEL SYSTEMS
18-21
-
AN INTEGRATED RISK INFORMED DECISION MAKING IN THE NUCLEAR INDUSTRY
22-34
-
ELEMENTS OF AUTOMATIC CONTROL OF HYDRODYNAMIC SYSTEMS
35-36
-
AUGMENTED REALITY – THE WAY TO USING ADVANCED TECHNOLOGY IN NORMAL LIFE
37-40
-
INDUCTANCE CALCULATION CONSIDERING MAGNETIC SATURATION OF INTERIOR PERMANENT MAGNET SYNCHRONOUS MACHINES
41-44
-
EXTENDED KALMAN FILTER AS A FULL STATE OBSERVER IN APPLICATION OF THE INERTIA WHEEL PENDULUM
45-48
Main Article Content
DOI
Authors
Abstract
The design of analog-to-digital converter implemented in CMOS 180 nm technology has been presented in this paper. The successive approximation architecture with charge redistribution has been chosen. Much emphasis was placed on limiting the area occupancy of the whole chip so as its power consumption, which makes the described circuit suitable for multichannel applications. The presented converter achieves 3 MS/s sampling rate with 7-bit resolution at 77 μW and occupies only 90 x 95 μm2.
Keywords:
SAR ADC, charge redistribution, successive approximation converter
Article Details
Otfinowski, P. ., Kmon, P., & Kłeczek, R. . (2013). DESIGN OF 7-BIT LOW-POWER, LOW AREA A/D CONVERTER IN SUBMICRON PROCESS FOR MULTICHANNEL SYSTEMS. Informatyka, Automatyka, Pomiary W Gospodarce I Ochronie Środowiska, 3(2), 18–21. https://doi.org/10.35784/iapgos.1447
